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Agilent HMMC-3128 DC-12 GHz Packaged High Efficiency Divide-by-8 Prescaler
1GC1-8208-TR1-7" diameter reel/500 each 1GC1-8208-BLK-bubble strip/10 each Data Sheet
Features
* Wide Frequency Range: 0.2-12 GHz * High Input Power Sensitivity: On-chip pre- and post-amps -15 to +10 dBm (1- 8 GHz) -10 to +8 dBm (8-10 GHz) -5 to +2 dBm (10-12 GHz) * Pout: 0 dBm (0.5 Vp-p) * Low Phase Noise: -153 dBc/Hz @ 100 kHz Offset * (+) or (-) Single Supply Bias Operation * Wide Bias Supply Range: 4.5 to 6.5 volt operating range * Differential I/0 with on-chip 50 matching
Package Type: Package Dimensions: Package Thickness: Lead Pitch: Lead Width:
8-lead SOIC Plastic 4.9 x 3.9 mm typ. 1.55 mm typ. 1.25 mm nom. 0.42 mm nom.
Absolute Maximum Ratings1
(@ TA = 25C, unless otherwise indicated) Symbol Parameters/Conditions Bias supply voltage Bias supply voltage Bias supply delta Logic threshold voltage CW RF input power DC input voltage (@ RFin or RFin ports) Backside operating temperature Storage temperature Maximum assembly temperature (60 s max.) -40 -65 -7 0 VCC -1.5 +7 VCC -1.2 +10 VCC 0.5 +85 +165 310 Min. Max. +7 Units volts volts volts volts dBm volts C C C
Description
The HMMC-3128 is a packaged GaAs HBT MMIC pre-scaler which offers dc to 12 GHz frequency translation for use in communications and EW systems incorporating high-frequency PLL oscillator circuits and signalpath down conversion applications. The prescaler provides a large input power sensitivity window and low phase noise.
VCC VEE VCC - VEE VLogic Pin(CW) VRFin TBS2 Tst Tmax
Notes 1. Operation in excess of any parameter limit (except TBS) may cause permanent damage to the device. 2. MTTF > 1 x 106 hours @ TBS 85C. Operation in excess of maximum operating temperature (TBS) will degrade MTTF.
DC Specifications/Physical Properties
(TA = 25C, VCC - VEE = 5.0 volts, unless otherwise listed) Symbol VCC - VEE |ICC| or |IEE| VRFin(q) VRFout(q) VLogic Parameters/Conditions Operating bias supply difference1 Bias supply current Quiescent dc voltage appearing at all RF ports Nominal ECL Logic Level (VLogic contact self-bias voltage, generated on-chip) Min. 4.5 37 Typ. 5.0 44 VCC Max. 6.5 51 Units volts mA volts
VCC -1.45
VCC -1.32
VCC -1.25
volts
Notes 1. Prescaler will operate over full specified supply voltage range, VCC or VEE not to exceed limits specified in Absolute Maximum Ratings section.
RF Specifications
(TA = 25C, Z0 = 50 , VCC - VEE = 5.0 volts) Symbol in(max) in(min) Self-Osc. Pin Parameters/Conditions Maximum input frequency of operation Minimum input frequency of operation1 (Pin = -10 dBm) Output Self-Oscillation Frequency2 @ dc, (Square-wave input) @ in = 500 MHz, (Sine-wave input) in = 1 to 8 GHz in = 8 to 10 GHz in = 10 to 12 GHz RL S12 N Jitter Tr or Tf Small-Signal Input/Output Return Loss (@ in < 10 GHz) Small-Signal Reverse Isolation (@ in < 10 GHz) SSB Phase noise (@ Pin = 0 dBm, 100 kHz offset from a out = 1.2 GHz Carrier) Input signal time variation @ zero-crossing (in = 10 GHz, Pin = -10 dBm) Output transition time (10% to 90% rise/fall time) -15 -15 -15 -10 -5 Min. 12 Typ. 14 0.2 3.4 > -25 > -20 > -20 > -15 > -10 15 30 -153 1 70 +10 +10 +10 +5 -1 0.5 Max. Units GHz GHz GHz dBm dBm dBm dBm dBm dB dB dBc/Hz ps ps
Notes 1. For sine-wave input signal. Prescaler will operate down to dc for square-wave input signal. Minimum divide frequency limited by input slew-rate. 2. Prescaler may exhibit this output signal under bias in the absence of an RF input signal. This condition may be eliminated by use of the Input dc offset technique described on page 4.
2
RF Specifications (Continued)
(TA = 25C, Z0 = 50 , VCC - VEE = 5.0 volts) Symbol Pout3 Parameters/Conditions @ out < 1 GHz @ out = 2.5 GHz @ out = 3.0 GHz |Vout(p-p)|4 @ out < 1 GHz @ out = 2.5 GHz @ out = 3.0 GHz PSpitback out power level appearing at RFin or RFin (@ in 10 GHz, unused RFout or RFout unterminated) out power level appearing at RFin or RFin (@ in = 10 GHz, both RFout & RFout terminated) Pfeedthru H2
Notes 3. Fundamental of output square wave's Fourier Series. 4. Square wave amplitude calculated from Pout.
Min. -2 -3.5 -4.5
Typ. 0 -1.5 -2.5 0.5 0.42 0.37 -50 -55 -30
Max.
Units dBm dBm dBm volts volts volts dBm dBm dBc
Power level of in appearing at RFout or RFout (@ in = 12 GHz, Pin = 0 dBm, referred to Pin (in)) Second harmonic distortion output level (@ out = 3.0 GHz, referred to Pout (out))
-25
dBc
Applications
The HMMC-3128 is designed for use in high frequency communications, microwave instrumentation, and EW radar systems where low phase-noise PLL control circuitry or broad-band frequency translation is required.
Operation
The device is designed to operate when driven with either a single-ended or differential sinusoidal input signal over a 200 MHz to 12 GHz bandwidth. Below 200 MHz the prescaler input is "slew-rate" limited, requiring fast rising and falling edge speeds to properly divide. The device will operate at frequencies down to dc when driven with a square-wave.
Due to the presence of an off-chip RF-bypass capacitor inside the package (connected to the VCC contact on the device), and the unique design of the device itself, the component may be biased from either a single positive or single negative supply bias. The backside of the package is not dc connected to any dc bias point on the device. For positive supply operation, VCC pins are nominally biased at any voltage in the +4.5 to +6.5 volt range with pin 8 (VEE) grounded. For negative bias operation VCC pins are typically grounded and a negative voltage between -4.5 to -6.5 volts is applied to pin 8 (VEE).
AC-Coupling and DC-Blocking
All RF ports are dc connected on-chip to the VCC contact through on-chip 50 resistors. Under any bias conditions where VCC is not dc grounded the RF ports should be ac coupled via series capacitors mounted on the PC board at each RF port. Only under bias conditions where VCC is dc grounded (as is typical for negative bias supply operation) may the RF ports be direct coupled to adjacent circuitry or in some cases, such as level shifting to subsequent stages. In the latter case the package heat sink may be "floated" and bias applied as the difference between VCC and VEE.
3
Input DC Offset
If an RF signal with sufficient signal to noise ratio is present at the RF input lead, the prescaler will operate and provide a divided output equal the input frequency divided by the divide modulus. Under certain "ideal" conditions where the input is well matched at the right input frequency, the component may "self-oscillate", especially under small signal input powers or with only noise present at the input. This "self-oscillation" will produce a undesired output signal also known as a false trigger. To prevent false triggers or self-oscillation conditions, apply a 20 to 100 mV dc offset voltage between the RFin and RFin ports. This prevents noise or spurious low level signals from triggering the divider. Adding a 10 k resistor between the unused RF input to a contact point at the VEE potential will result in an offset of 25 mV between the RF inputs. Note however, that the input sensitivity will be reduced slightly due to the presence of this offset.
Figure 1. Simplified Schematic
unused RF output lead should be terminated into 50 to a contact point at the VCC potential or to RF ground through a dc blocking capacitor. A minimum RF and thermal PC board contact area equal to or greater than 2.67 x 1.65 mm (0.105" x 0.065") with eight 0.020" diameter plated-wall thermal vias is recommended.
MMIC ESD precautions, handling considerations, die attach and bonding methods are critical factors in successful GaAs MMIC performance and reliability. Agilent application note #54, "GaAs MMIC ESD, Die Attach and Bonding Guidelines" provides basic information on these subjects. Moisture Sensitivity Classification: Class 1, per JESD22-A112-A.
Assembly Notes
Independent of the bias applied to the package, the backside of the package should always be connected to both a good RF ground plane and a good thermal heat sinking region on the PC board to optimize performance. For single-ended output operation the
Additional References:
PN #18, "HBT Prescaler Evaluation Board."
4
Symbol
A A1 B C D E e H L a
Min.
1.35 0.0 0.33 0.19 4.80 3.80 1.27 BSC 5.80 0.40 0
Max.
1.75 .25 0.51 .025 5.00 4.00 1.27 BSC 6.20 1.27 8
Notes:
* * * * All dimensions in millimeters. Refer to JEDEC Outline MS-012 for additional tolerances. Exposed heat slug area on package bottom = 2.67 x 1.65. Exposed heat sink on package bottom must be soldered to PCB RF ground plane.
Figure 2. Package and dimensions
Figure 3. Assembly diagram (Single-supply, positive-bias configuration shown)
5
Figure 4. Typical input sensitivity window
Figure 5. Typical supply current & VLogic vs. supply voltage
Figure 6. Typical phase noise performance
Figure 7. Typical output power vs. output frequency, out (GHz)
Figure 8. Typical "Spitback" power P(out) appearing at RF input port
6
Device Orientation
Tape Dimensions and Product Orientation
Notes:
1. 2. 3. 4. 5. 6. 10 sprocket hole pitch cumulative tolerance: 0.2 mm. Camber not to exceed 1 mm in 100 mm. Material: Black Conductive Advantek Polystyrene. Ao and Bo measured on a plane 0.3 mm above the bottom of the pocket. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
7
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This data sheet contains a variety of typical and guaranteed performance data. The information supplied should not be interpreted as a complete list of circuit specifi cations. Customers considering the use of this, or other Agilent GaAs ICs, for their design should obtain the current production specifi cations from Agilent. In this data sheet the term typical refers to the 50th percentile performance. For additional information contact Agilent MMIC_Helpline@agilent.com.
Product specifications and descriptions in this document subject to change without notice. (c) Agilent Technologies, Inc. 2007 Printed in USA, November 26, 2007 5989-7354EN

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